1. Field of the Invention
The present invention relates to a bootstrap circuit used in a shift register circuit and an output buffer circuit.
2. Description of the Related Art
A shift register circuit is widely used as a scan circuit or a matrix array driving circuit in a display apparatus and a semiconductor memory apparatus.
At the output stage of a shift register circuit, a push-pull output circuit is generally used. If the push-pull output circuit is configured by making use of only transistors of the same conduction type, however, the output voltage of the push-pull output circuit cannot be assured sufficiently. If the push-pull output circuit is configured by making use of only transistors which are each created as a transistor of the n-channel type for example, a difference Vgs in electric potential between a gate electrode and a source area in a transistor provided on the high electric-potential side of the push-pull output circuit drops as the output voltage of the push-pull output circuit rises. For Vgs<Vth where reference notation Vth denotes the threshold voltage of the transistor, the transistor is in a turned-off state. Thus, the push-pull output circuit generates the output voltage only for a range of (Vgs−Vth). In order to solve this problem, there has been proposed an output circuit which makes use of a bootstrap operation.
As a shift register circuit making use of a bootstrap operation, Japanese Patent Laid-open No. Hei 10-112645 used as Patent Document 1 in this patent specification discloses a transistor circuit having a typical configuration shown in a circuit diagram of FIG. 25. As shown in the circuit diagram of FIG. 25, the typical configuration basically employs three transistors per stage. In the case of the typical configuration shown in the circuit diagram of FIG. 25, three transistors Tr1, Tr2 and Tr3 of typically the n-channel type are employed at every stage of the configuration.
The shift register circuit having a typical configuration shown in the circuit diagram of FIG. 25 is explained as follows. FIG. 26A is a circuit diagram showing a typical configuration of a bootstrap circuit provided at the first stage of the shift register circuit whereas FIG. 26B is a timing diagram showing a model of timing charts of signals relevant to operations carried out by the bootstrap circuit shown in the circuit diagram of FIG. 26A. By paying attention to the first stage of the shift register circuit shown in the circuit diagram of FIG. 26A, the reader will be aware of the fact that a first transistor Tr1 and a second transistor Tr2 together compose a push-pull output circuit. A specific one of the source and drain areas of the first transistor Tr1 and a specific one of the source and drain areas of the second transistor Tr2 are connected to each other by an output section OUT1 of the bootstrap circuit provided at the first stage. A transistor has two areas, i.e., source and drain areas which are referred to as a specific one of the source and drain areas and the other one of the source and drain areas respectively in this patent specification. By the same token, two clock signals having phases different from each other are referred to as a specific one of the clock signals and the other one of the clock signals respectively in this patent specification.
The other one of the source and drain areas of the first transistor Tr1 is connected to a clock supply line which conveys a specific one of the two clock signals CK1 and CK2 having phases different from each other as shown in the timing diagram of FIG. 26B. In the case of the first stage of the typical shift register circuit shown in the circuit diagram of FIG. 26A, the specific one of the two clock signals CK1 and CK2 is the clock signal CK1. The other one of the source and drain areas of the second transistor Tr2 is connected to a first voltage supply line conveying a first voltage Vss which is set typically at a low level of 0 V. The gate electrode of the first transistor Tr1 and a specific one of the source and drain areas of the third transistor Tr3 are connected to each other by a node section P1. The gate electrodes of the second transistor Tr2 and the third transistor Tr3 are connected to a clock supply line conveying the other one of the two clock signals CK1 and CK2. In the case of the first stage of the typical shift register circuit shown in the circuit diagram of FIG. 26A, the other one of the two clock signals CK1 and CK2 is thus the clock signal CK2. The other one of the source and drain areas of the third transistor Tr3 is connected to a signal supply line which conveys an input signal IN1.
It is to be noted that, between the gate electrode of the first transistor Tr1 and the specific one of the source and drain areas of the first transistor Tr1, between the gate electrode of the first transistor Tr1 and the other one of the source and drain areas of the first transistor Tr1 or between the gate electrode of the first transistor Tr1 and the specific one of the source and drain areas of the first transistor Tr1 as well as between the gate electrode of the first transistor Tr1 and the other one of the source and drain areas of the first transistor Tr1, a capacitor serving as bootstrap capacitor may be connected in some cases. In the case of the first stage of the typical shift register circuit shown in the circuit diagram of FIG. 25 or 26A, a capacitor Ca serving as bootstrap capacitor is connected between the gate electrode of the first transistor Tr1 and the specific one of the source and drain areas of the first transistor Tr1. Typically, the bootstrap capacitor Ca is composed of two conductive layers sandwiching an insulation layer. As an alternative, the bootstrap capacitor Ca can also be the so-called MOS (Metal Oxide Semiconductor) capacitor.
By referring to the timing charts shown in the timing diagram of FIG. 26B, operations carried out by the first stage of the typical shift register circuit are explained as follows. It is to be noted that the high level of each of the two clock signals CK1 and CK2 having phases different from each other and the input signal IN1 is a second voltage Vdd which is set typically at 5 V. On the other hand, the low level of each of these signals is the aforementioned first voltage Vss which is set typically at 0 V as described above. In the following description, reference notation Vthi denotes the threshold voltage of an ith transistor. For example, reference notation Vth3 denotes the threshold voltage of the third transistor Tr3.
Time Period T1 
In the time period T1, each of the input signal IN1 and the first clock signal CK1 is set at a low level whereas the second clock signal CK2 is set at a high level. The input signal IN1 set at the low level is supplied to the gate electrode of the first transistor Tr1 by way of the third transistor Tr3 which is in a turned-on state. Thus, the electric potential appearing at the gate electrode of the first transistor Tr1 and the node section P1 is also set at the low level, putting the first transistor Tr1 in a turned-off state. Since the second clock signal CK2 is set at a high level, on the other hand, the second transistor Tr2 is put in a turned-on state as the third transistor Tr3 is. Thus, the output section OUT1 is pulled down by the second transistor Tr2 put in a turned-on state to the first voltage Vss which is a voltage at a low level.
Time Period T2 
In the time period T2, the first clock signal CK1 is set at the high level whereas the second clock signal CK2 is set at the low level. Since the third transistor Tr3 is put in a turned-off state, the node section P1 is put in a floating state of holding the electric potential which has been set during the time period T1. That is to say, the node section P1 is put in a floating state of sustaining the electric potential which has been set at the low level. Thus, the first transistor Tr1 is maintaining the turned-off state. On the other hand, the state of the second transistor Tr2 is changed from the turned-on state to the turned-off state. As a result, the output section OUT1 is put in a floating state of being connected to a capacitive load which is not shown in the circuit diagram of FIG. 26A. That is to say, the output section OUT1 is sustaining the electric potential which has been set at the low level during the time period T1.
Time Period T3 
In the time period T3, each of the input signal IN1 and the second clock signal CK2 is set at the high level whereas the first clock signal CK1 is set at the low level. The third transistor Tr3 is put in a turned-on state, supplying the input signal IN1 set at the high level to the node section P1. Thus, the electric potential appearing on the node section P1 rises. As the electric potential appearing on the node section P1 attains an electric potential of (Vdd−Vth3), the third transistor Tr3 is put in a turned-off state, putting the node section P1 in a floating state of holding the electric potential of (Vdd Vth3). Each of the first transistor Tr1 and the second transistor Tr2 is in a turned-on state. The first clock signal CK1 set at the same low level as the first voltage Vss is supplied to the other one of the source and drain areas of the first transistor Tr1. The other one of the source and drain areas of the second transistor Tr2 is also connected to a first voltage supply line which conveys the first voltage V. Thus, the first voltage Vs, appears on the output section OUT1, setting the output section OUT1 at a low level.
Time Period T4 
In the time period T4, the first clock signal CK1 is set at the high level whereas each of the input signal IN1 and the second clock signal CK2 is set at the low level. Since the second clock signal CK2 is set at the low level, each of the second transistor Tr2 and the third transistor Tr3 is in a turned-off state. The node section P1 is put in a floating state whereas the first transistor Tr1 is put in a turned-on state. Thus, the first transistor Tr1 connects the output section OUT1 to the first clock supply line conveying the first clock signal CK1 set at the high level, raising the electric potential appearing on the output section OUT1. At that time, due to a bootstrap operation through a bootstrap capacitor such as the gate capacitor of the first transistor Tr1, the electric potential appearing on the node section P1 rises to a level at least equal to the second voltage Vdd. Thus, the second voltage Vdd is output as the high level of the output section OUT1.
Time Period T5 
In the time period T5, each of the input signal IN1 and the first clock signal CK1 is set at the low level whereas the second clock signal CK2 is set at the high level. When the second clock signal CK2 is set at the high level, each of the second transistor Tr2 and the third transistor Tr3 is put in a turned-on state. The second transistor Tr2 put in a turned-on state connects the output section OUT1 to the first voltage supply line conveying the first voltage Vss. Thus, the output section OUT1 is reset to the low level. On the other hand, the third transistor Tr3 put in a turned-on state connects the node section P1 to the input signal IN1 which is set at the low level. Thus, the node section P1 is also reset to the low level.
Time Period T6 
In the time period T6, the first clock signal CK1 is set at the high level whereas each of the input signal IN1 and the second clock signal CK2 is set at the low level. The operation carried out in the time period T6 is basically the same as the operation carried out in the time period T2. Since the third transistor Tr3 is put in a turned-off state, the node section P1 is put in a floating state of holding the electric potential set at the low level. Thus, the first transistor Tr1 is maintaining the turned-off state. On the other hand, the state of the second transistor Tr2 is changed from the turned-on state to the turned-off state. As a result, the output section OUT1 is sustaining the electric potential set at the low level.